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| NJU6682 PRELIMINARY 160-common x 132-segment DOT MATRIX LCD DRIVER FOR 4 GRAY SCALE sGENERAL DESCRIPTION The NJU6682 is a bit map LCD driver to display graphics or characters. It contains 84,480 bits display data RAM, microprocessor interface circuits, instruction decoder, and 160-common and 132-segment drivers. The bit image data is transferred to the internal display data RAM by serial interface or 8-bit/16-bit parallel interface. The NJU6682 features 4-gray scale function which creates 4 types gray scale (for example : white/light gray/dark gray/black) or black & white with displays 160 x 132 dots graphics or 8-caracter 10line by 16 x 16 dots characters. It oscillates by built-in OSC circuit without any external components. Furthermore, the NJU6682 features Partial Display Function which creates up to 2 blocks of active display area and optimizes duty cycle ratio. This function sets optimum boosted voltage by the combination with both of programmable voltage booster circuit and electrical variable resister. As result, it reduces the operating current. The operating voltage from 2.4V to 3.3V and low operating current are useful for small size battery operating items. sPACKAGE OUTLINE NJU6682CH sFEATURES qDirect Correspondence between Display Data RAM and LCD Pixel qDisplay Data RAM - 84,480 bits ;( 160-Com x 132-Seg) x 2-area ) x 2bit ....2 times over than display size qDisplay Method - Monochrome 4-Gray Scale / Black & White qPartial Display Function ( 2 blocks of active display area and automatic duty cycle ratio selection ) qVariable RAM Mapping - The display screen can be composed from the RAM area in a maximum of 8 blocks not to continue. qEasy Vertical Scroll by the variable start line address and over size display data RAM (This function doesn't work in Variable RAM Mapping mode ) qLCD drivers - 160-common and 132-segment qDirect 8-bit / 16-bit Microprocessor interface for both of 68 type and 80 type MPU qSerial Interface qProgrammable Bias selection ; 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14 bias qCommon Driver Order Assignment by mask option Version C0 to C159( Pin Name ) NJU6682A COM0 to COM159 NJU6682B COM159 to COM0 qUseful Instruction Set Display Data Read/Write, Display ON/OFF, Z-Address Set, X-Address Set, Y-Address Set, Status Read, Normal or Inverse ON/OFF, Static Drive ON/OFF, Partial Display, n-Line Inverse, EVR Resister Set, Variable RAM Mapping Mode, Gray Scale Level Select, Bias Select, Voltage Converter Multiple Select ( 7-times maximum ), Read Modify Write, Reset ,Internal Power Supply, Driver Outputs ON/OFF, Power Save, ADC Select, Display Mode Select, 8-bit / 16-bit Buss Select, etc. qPower Supply Circuit for LCD; Programmable Booster Circuits( 7-time maximum ), Regulator, Voltage Follower x 4 qPrecision Electrical Variable Resistance qLow Power Consumption T.B.D ( typ. ) qOperating Voltage 2.4 to 3.3 V qLCD Driving Voltage 6.0 to 18.0V qPackage Outline Bumped Chip / TCP qC-MOS Technology MAY 2000 Ver-1.3 NJU6682 sPAD LOCATION S81 S80 C158 C159 S131 S130 C80 C81 S79 S78 C79 C78 Y X S1 S0 C1 C0 Chip Center Chip Size Chip Thickness Bump Size Pad Pitch Bump Heght Bump Material VDD V1 V2 V3 V4 V5 VR VDD C1+ C1+ C2 C2C3C4C5C6VOUT VSS D15 D14 D13 D12 D11 D10 D9 D8 D7(SI) D6(SCL) D5 D4 D3 D2 D1 D0 RD WR A0 CS OSC2 OSC1 VSS RES SEL68 PS0 PS1 DUMMY2 DUMMY1 DUMMY0 VDD :X=0um,Y=0um :X=8.27m,Y=5.67mm :675um 30um :45um x 83um :60um (min) :15um (typ) :Au NJU6682 s PAD Cordinates Chip Size 8.27x5.67mm(Chip Center X=0um, Y=0um) PAD No. Terminal X(um) Y(um) 51 C1 3975 -2126 52 C2 3975 -2066 53 C3 3975 -2006 54 C4 3975 -1946 55 C5 3975 -1886 56 C6 3975 -1826 57 C7 3975 -1766 58 C8 3975 -1706 59 C9 3975 -1646 60 C10 3975 -1586 61 C11 3975 -1526 62 C12 3975 -1466 63 C13 3975 -1406 64 C14 3975 -1346 65 C15 3975 -1286 66 C16 3975 -1226 67 C17 3975 -1166 68 C18 3975 -1106 69 C19 3975 -1046 70 C20 3975 -986 71 C21 3975 -926 72 C22 3975 -866 73 C23 3975 -806 74 C24 3975 -746 75 C25 3975 -686 76 C26 3975 -626 77 C27 3975 -566 78 C28 3975 -506 79 C29 3975 -446 80 C30 3975 -386 81 C31 3975 -326 82 C32 3975 -266 83 C33 3975 -206 84 C34 3975 -146 85 C35 3975 -86 86 C36 3975 -26 87 C37 3975 34 88 C38 3975 94 89 C39 3975 154 90 C40 3975 214 91 C41 3975 274 92 C42 3975 334 93 C43 3975 394 94 C44 3975 454 95 C45 3975 514 96 C46 3975 574 97 C47 3975 634 98 C48 3975 694 99 C49 3975 754 100 C50 3975 814 PAD No. Terminal 1 VDD 2 DUMMY0 3 DUMMY1 4 DUMMY2 5 PS1 6 PS0 7 SEL68 8 RES 9 VSS 10 OSC1 11 OSC2 12 CS 13 A0 14 WR 15 RD 16 D0 17 D1 18 D2 19 D3 20 D4 21 D5 22 D6(SCL) 23 D7(SI) 24 D8 25 D9 26 D10 27 D11 28 D12 29 D13 30 D14 31 D15 32 VSS 33 VOUT 34 C6 35 C5 36 C4 37 C3 38 C2 + 39 C2 40 C1 + 41 C1 42 VDD 43 VR 44 V5 45 V4 46 V3 47 V2 48 V1 49 VDD 50 C0 X(um) -3933 -3863 -3793 -3723 -3562 -3325 -3105 -2869 -2712 -2555 -2319 -2098 -1862 -1641 -1405 -1168 -948 -727 -507 -287 -66 153 374 594 814 1035 1255 1476 1696 1916 2137 2298 2368 2464 2613 2683 2832 2902 3050 3120 3269 3339 3519 3589 3659 3729 3799 3869 3939 3975 Y(um) -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2186 NJU6682 PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Terminal C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 X(um) 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 Y(um) 874 934 994 1054 1114 1174 1234 1294 1354 1414 1474 1534 1594 1654 1714 1774 1834 1894 1954 2014 2074 2134 2194 2254 2314 2374 2434 2494 2554 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Terminal C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 X(um) 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 Y(um) 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 NJU6682 PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Terminal C151 C152 C153 C154 C155 C156 C157 C158 C159 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 X(um) -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 Y(um) 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Terminal S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 X(um) -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 Y(um) 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2517 2457 2397 2337 2277 2217 2157 2097 2037 1977 1917 1857 1797 1737 1677 1617 1557 1497 1437 1377 1317 1257 1197 1137 1077 1017 957 897 837 777 717 657 597 537 477 417 357 297 237 NJU6682 PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 Terminal S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 X(um) -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 Y(um) 177 117 57 -2 -62 -122 -182 -242 -302 -362 -422 -482 -542 -602 -662 -722 -782 -842 -902 -962 -1022 -1082 -1142 -1202 -1262 -1322 -1382 -1442 -1502 -1562 -1622 -1682 -1742 -1802 -1862 -1922 -1982 -2042 -2102 -2162 -2222 NJU6682 sBLOCK DIAGRAM S0 Vss Vdd V1toV5 5 C1+ C1C2+ C2C3C4C5C6VR Voltage Generator Output Assignment Resister 132 Shift Register S131 C0 C159 SEG Driver COM Driver Common Timing Generator Gray Scale/Black & White Control 132 x 2 Display Data Latch Y Address Decoder Z Address Decoder FRC/PWM Controler Display Timing Generator Display Data RAM 132 x 2 x 160 x 2 Y Address Resister I/O Buffer X Address Decoder X Address Counter X Address Resister Multiplexer 6bit 6bit OSC OSC1 OSC2 I/O Buffer Status Instruction Decoder Internal Bus BF Bus Holder Reset MPU Interface RES CS A0 RD WR SEL68 P/S0 P/S1 Z Register Z Counter D0toD5 D8toD15 D6(SCL) D7(SI) NJU6682 sTERMINAL DESCRIPTION No. 2 to 4 1,42,49 9,32 Symbol DUMMY VDD VSS I/O Function Dummy Terminals. These terminals are insulated. 2.4V to 3.3V GND LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not used, supply each level of LCD driving voltage from outside with following relation. Power GND VDDV1V2V3V4V5 When the internal power supply is used, the internal circuits generate and supply following LCD bias voltage from V1 to V4 terminals. 48 47 46 45 44 V1 V2 V3 V4 V5 Bias 1/4Bias 1/5Bias 1/6Bias 1/7Bias 1/8Bias 1/9Bias 1/10Bias 1/11Bias 1/12Bias 1/13Bias 1/14Bias V1 V5+3/4Vlcd V5+4/5Vlcd V5+5/6Vlcd V5+6/7Vlcd V5+7/8Vlcd V5+8/9Vlcd V5+9/10Vlcd V5+10/11Vlcd V5+11/12Vlcd V5+12/13Vlcd V5+13/14Vlcd V2 V5+2/4Vlcd V5+3/5Vlcd V5+4/6Vlcd V5+5/7Vlcd V5+6/8Vlcd V5+7/9Vlcd V5+8/10Vlcd V5+9/11Vlcd V5+10/12Vlcd V5+11/13Vlcd V5+12/14Vlcd V3 V5+2/4Vlcd V5+2/5Vlcd V5+2/6Vlcd V5+2/7Vlcd V5+2/8Vlcd V5+2/9Vlcd V5+2/10Vlcd V5+2/11Vlcd V5+2/12Vlcd V5+2/13Vlcd V5+2/14Vlcd V4 V5+1/4Vlcd V5+1/5Vlcd V5+1/6Vlcd V5+1/7Vlcd V5+1/8Vlcd V5+1/9Vlcd V5+1/10Vlcd V5+1/11Vlcd V5+1/12Vlcd V5+1/13Vlcd V5+1/14Vlcd (Vlcd=Vdd-V5) Power 41 40 39 38 37 36 35 34 33 43 C1+ C1C2+ C2C3C4C5C6VOUT VR O Step up capacitor connecting terminals. Voltage booster circuit ( adjustable with 2 to 7 times ) O I Step up voltage output terminal. Connect the step up capacitor between this terminal and VSS. Voltage adjust terminal. V5 level is adjusted by external bleeder resistance connecting between VDD and V5 terminal. ( P/S="H" )In Pararel Interface Mode *8-bit bus mode*1: I/O terminals for 8-bit bus. *16-bit bus mode*1: I/O terminals for the 8-bits of lower ranks of 16-bit bus. * To set these 8-bit / 16-bit mode, use Instruction " 8-bit / 16-bit Bus 1 16 to 23 (23) (22) D0 to D7 (SI) (SCL) Select ". I/O ( P/S="L" )In Serial Interface Mode *D7: Input terminal for serial data ( SI ). *D6: Input terminal for serial data clock ( SCL ). When select these mode, D0 to D5 will be Hi-Z status. ( CS="H" ) D0 to D7 shown Hi-Z. NJU6682 No. 24 to 30 Symbol D8 to D15 I/O Function 8-bit Bus Mode & Serial Mode *Output terminal with Hi-Z status. 16-bit Bus Mode *I/O terminals for the upper 8-bits of 16-bit bus. Normaly, connect to the address bus of MPU. The data on the D0 to D7 is distinguished as Display Data or Instruction by status of A0. PS1 terminal H PS0 terminal Ao terminal H L H L Distinction Display Data Instruction Display Data Instruction The 17th data of serial data is recognized as A0. I/O H 13 A0 I L L : H or L 8 12 RES CS RD 15 (E) I I I I Reset terminal. When the RES terminal goes to "L", the initialization is performed. Reset operation is executing during "L" state of RES. Chip serect terminal. Data Input/Output are available during CS="L". < In case of 80 type MPU ( PS1="H", SEL68="L" ) > RD signal of 80 type MPU input terminal. Active "L". During this signal is "L", D0 to D7 terminals are output. < In case of 68 type MPU ( PS1="H", SEL68="H" ) > Enable signal of 68 type MPU input terminal. Active "H". < In case of 80 type MPU ( PS1="H", SEL68="L" ) > Connect to the 80 type MPU WR signal. Active "L". The data on the data bus input syncronizeing the rise edge of this terminal. < In case of 68 type MPU ( PS1="H", SEL68="H" ) > The read / Write control signal of 68 type MPU input terminal. (R/W) I R/W State H Read L Write WR 14 I MPU interface type selection terminal. 7 SEL68 I SEL68 State H 68 type L 80 type Serial or parallel type interface selection terminal. PS1 "H" PS0 "H" "L" "L" Interface Parallel Serial 4-wire Serial 3-wire Chip Select CS CS CS Data/ Command A0 A0 The 17th data of serial data is recognized as A0. Data RD WR SI(D7) SI(D7) Read/ Write Write Only Write Only Write Only Serial Clock SCL (D6) SCL (D6) 6 5 PS0 PS1 I 10 11 OSC1 OSC2 I/O *In case of serial interface ( PS1=0 ), RD and WR must be fixed to "H" or "L", and D0 to D5 will be Hi-Z. System clock input terminal for Maker testing. ( This terminal should be Open ) For external clock operation, the clock should be input to OSC1 terminal. NJU6682 No 50 to 209 Symbol C0 to C159 I/O Function LCD driving signal output terminal. *Common output terminal :C0 to C159 *Segment output terminal :S0 to S131 *Segment output terminal The following output voltage are selected by the combination of FR and data in the RAM. Alternating Sn OutPut Voltage RAM Data Signal Disp. Positive Disp. Negative H VDD V2 H L V5 V3 H V2 VDD L L V3 V5 *Common output terminal The following output voltage are selected by the combination of FR and status of common. Scan Data H L Alternating Signal H L H L COn Output Voltage V5 VDD V1 V4 O 341 to 210 S0 to S131 NJU6682 Functional Description (1)Description for each blocks 1-1) Busy Flag (BF) As for NJU6682, in case of the inner operation, busy flag (BF) doesn't accept an instruction except of "1". In the status reed instruction, a busy flag is output by the D7 terminal. If cycle time (tcyc) is secured, to check this flag in front of the instruction isn't necessary and the throughput of the CPU can be substantially improved. 1-2) X-Address Counter The X-address counter is the 6 bit presettable counter which gives an address for the row of the display data RAM as shown in figure 1 and is done in +1 increment by the execution of the display data read / write instruction. But, when the X-address counter reaches the maximum of the exist address, the count locks by the X-address counter. With to set X-address once again, as for the count lock of cancellation again this counter is independent with Y-address register. By the address inverse instruction(ADC), it is possible for X-address decoder to reverse correspondence relation between X-address and segment output of display data RAM. 1-3)Z-Address counter The Y-address counter generates an address to the display RAM direction of the line, it is reset when the inner FR signal switching timing and count up synchronizes with common cycle of NJU6682. 1-4)Y-Address Register Y-address register is which gives an address to the display data RAM direction of the line as shown in figure 1. When replacing Y-address from the CPU and accessing to them, it does by the instruction of the set of Y-address. 1-5)Z-Address Register Z-address register can be generally used for the scrolling of a screen, in addition to the display with the register which sets the low address of the data RAM which corresponds to the display line ( being the best line generally ) of COM0. It sets a display beginning line by setting the display beginning address of 9 bits in this register by the instruction of the set of Z-address. 1-6)Display data RAM Display data RAM is the bit map RAM which stores the data for the display which corresponds to the LCD pixel and is composed of 84,480 bits. Each bit of the display data RAM corresponds to 2:1 in case of gray scale display to each pixel of LCD and in case of Black and White display, it corresponds to 1:1. The relation between the display data and the LCD in case of gray scale display is as follows. The relation between Display data and LCD in Gray Scale Display The Display RAM data : "00" = Gray Scale Level 0 ( setting by the gray scale level select ) The Display RAM data : "01" = Gray Scale Level 1 ( " ) The Display RAM data : "10" = Gray Scale Level 2 ( " ) The Display RAM data : "11" = Gray Scale Level 3 ( " ) The relation between Display data and LCD in Black and White Display In Positive Display : "1"=Turn-On Display,"0" =Turn-Off Display In Negative Display: "1"=Turn-Off Display,"0" =Turn-On Display When the Display method chooses 16 bit access by the gray scale display, because RAM area of X-address = 16 become 8 bits, lower 8bit (D7-D0) is ignored ( Figure 1-1 ). When the display method chooses 16 bit access by the Black and White display, as for RAM area of X-address = 8 (Layer0) or 40 (Layer1) becomes 4-bits, lower 12 bit (D11-D0) is ignored. The bus with in access to the Display Data RAM is 8-bit access an d 16-bit access with the 8-bit / 16-bit Bus Select instruction. The access can be chosen. Sn X Address ADC=1 ADC=0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 138 139 13A 13B 13C 13D 13E 13F Y Address Output 0 1 10H (010000) 2 3 00H (000000) 4 5 6 0FH (001111) 7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Correspondence with Display Data RAM Address ( in gray scale mode) Fig.1-1 0FH (000000) 0 (000000) 10H (010000) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 124 125 126 127 128 129 130 NJU6682 131 Sn X Address ADC=1 8H (001000) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 138 139 13A 13B 13C 13D 13E 13F Y address Output ADC=0 0 1 2 3 4 5 6 7 0H (000000) 7H (000111) D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Layer 0 7H (000111) 0H (000000) 8H (001000) 124 125 126 127 128 129 130 131 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 Correspondence with Display Data RAM Address ( in black & white mode) Fig.1-1 28H (101000) 0 1 2 3 4 5 6 7 20H (100000) 27H (100111) D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Layer 1 27H (100111) NJU6682 20H (100000) 28H (101000) 124 125 126 127 128 129 130 131 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 NJU6682 1-7)Output Assignment Register This circuit can choose the direction of the scan of the common output. Table1 Common Output Terminal PAD No. 50 Terminal C0 Name Ver. A COM0 Ver. B COM159 209 C159 COM159 COM0 *Able to be changed with the mask option of it by the choice (version A or B) to the common scan direction. 1-8)Reset Circuit This reset circuit does following initialization when the RES input becomes "L" level. *The initialization condition (The default setting) 1.It sets a display method in the 4 Gray Scale Display Mode. 2.Display Off 3.Display Positive 4.ADC select ; Positive 5.Read Modify Write 6.Voltage Booster off, Voltage Regulator off, Voltage follower off 7.Static Drive off 8.Driver output off 9.Clear the register data of serial interface 10.Set the X-address counter to (00)h 11.Set the Y-Address register to (00)h 12.Set the Z-Address at (00)h 13.The continuous RAM address(Variable RAM Mapping Mode) 14.Set the EVR register to (FF)h 15.Set the Duty 1/160 (Whole Display On) 16.Bias select D3,2,1,0="1,0,1,0" (1/14 Bias) 17.Voltage Booster Select D2,1,0,="1,0,1" ((7 times) 18.Set n-line inverting register to (0)h 19.Set to 8 Bit bus interface mode To be in " the MPU interface ( the reference example ) ", the RES terminal make connect with the reset terminal of the MPU and does at the same time as a MPU is initialized. The reset signal must put "L" pulse above minimum 10us to be in the clause of " the DC characteristic ". The RES signal becomes an operation condition generally after 1us from the rise-up edge. When not using a built-in LCD power supply circuit in NJU6682, in case of the outside liquid crystal power supply turning on, it is necessary to be RES="L". It clears each register by RES="L" and it is set in the above initialization condition but it doesn't have an influence about the oscillation circuit and output terminal (D0-D15). When initialization by the RES terminal isn't accomplished in power supply impressing, it sometimes enters the condition about which it is impossible to cancel. When using a reset instruction, 9 - 19 of the above initialization are executed. NJU6682 1-9)The LCD drive circuit system 1-9-1)The LCD drive circuit The common output has a shift register and it forwards a common scan signal in order. It outputs liquid crystal drive voltage in the combination of the display data, the common scan signal, the inner FR signal, the liquid crystal flowing mutually signal. A segment, common output corrugated example are shown in figure 2. 1-9-2)Display Data Latch-Circuit The display data latch circuit is the latch which stores the display data of 132 x 2 bits which are addressed by the Z-address counter and are output from the display data RAM to the LCD drive circuit every 1 common 1 period temporarily. Data in the display data RAM is changed and not held because display turn to Positive / Negative ( In case of Black & White display ),displaying on / off, Static Drive On / Off instructions are controls data in this latch circuit. 1-9-3)Gray Scale / Black & White Control Circuit A Gray Scale control circuit chooses the gray scale level which was set by the command instruction from the gray scale data of 264 bits which latched with the display data latch circuit and is output for LCD drive output Sn. A Black & White display control circuit chooses layer which was set by the command instruction from the 264 bit Black & White data which latched with the display data latch circuit and is output for LCD drive output Sn. 1-9-4)Z-Counter, Signal Genelate of Display Data Latch Circuit It generates a latch signal to the clock(CL) to Z-counter and to the display data latch circuit. It synchronizes with the internal display clock and the line address of the display data RAM occurs, and the display data of 132 x 2 bits synchronizes with the display clock, latches by the display data latch circuit and is output by the gray scale control / Black & White display control circuit. The read out to the display data LCD drive circuit is independent totally with the access to the display data RAM from the CPU. 1-9-5)Display Timing Genelate Circuit The display timing occurrence circuit generates the internal timing of the display system by the master clock and the internal FR signal. As for it, the internal FR signal and the LCD flowing mutually signal make the drive corrugation of the 2 frame alternating current drive or the n-line inverting drive method occur to the LCD Driving circuit. 1-9-6)FRC / PWM Control Circuit PWM & FRC(Frame Rate Control) to realize 4Gray Scale display function. NJU6682 1-9-7)Common Timing Genegation The common timing is generated by display clock CL ( refer to Fig. x 2 frame alternating current drive mode 159 160 CL 1 2 3 4 5 6 7 8 158 159 160 1 2 3 4 5 6 7 ) FR Vdd V1 C0 V4 V5 Vdd V1 C1 V4 V5 RAM DATA Vdd V2 Sn V3 V5 y n-line inverting drive mode 1 2 3 4 5 6 7 8 158 159 160 1 2 3 4 5 6 7 159 160 CL FR Vdd V1 C0 V4 V5 Vdd V1 C1 V4 V5 RAM DATA Vdd V2 Sn V3 V5 Fig.2 Waveform of Display Timing NJU6682 1-9-8)Oscillation Circuits The Oscillation Circuit is a low power CR oscillator incorporating with a Resistor and a Capacitor. it generates clocks for display timing signal source and the clock for step up circuits for LCD driving. The oscillation circuit output frequency is divided as display clock CL. Table 3 Duty Divide 1/4 1/1200 1/8 1/600 1/12 1/400 1/16 1/300 1/20 1/240 1/24 1/200 1/28 1/170 1/32 1/150 1/36 1/135 1/40 1/120 1/44, 1/48 1/105 1/52, 1/56 1/90 Duty Divide Duty Divide 1/60, 1/64, 1/68 1/75 1/72, 1/76, 1/80, 1/84, 1/88 1/60 1/92, 1/96, 1/100, 1/104, 1/108, 1/112, 1/116, 1/120 1/45 1/124, 1/128, 1/132, 1/136, 1/140, 1/144, 1/148, 1/152, 1/156, 1/160 1/30 1-9-9)Power Supply Circuits Internal Power Supply Circuit generates voltage for LCD driving. The power supply circuits consists of Step Up Circuits ( 2 times to 7 times ), Regulator Circuits, and Voltage Followers. The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size LCD panel application, please supply the external. The suitable value of the capacitors connecting to the V1 to V5 terminals and the step up circuit, and the feedback resistors for V5 operational amplifier depend on the LCD panel. And the power consumption with the LCD panel is depending on the display pattern. Please evaluate with actual LCD module. The operation of Internal Power Supply Circuits is controlled by the Internal Power Supply Control Instruction. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 DC D1 VR D0 VF *:Don't Care DC : Step Up Circuit DC=1 : Step Up Circuit ON DC=0 : Step Up Circuit OFF ( In this time, terminals C1+,C1-,C2+,C2-,C3-,C4-,C5- and C6- should be open, and VOUT should be supplied from outside. ) VR : Regulator Circuit VR=1 : Regulator Circuit ON VR=0 : Regulator Circuit OFF ( In this time, terminal VR should be open, and V5 should be supplied from outside. ) VF : Voltage Follower VR=1 : Voltage Follower ON VR=0 : Voltage Follower OFF ( In this time, terminals V1 to V5 should be supplied from outside. ) NJU6682 Examples for application circuits of the internal Power Supply xNone of the internal power supply functions ( DC,VR,VF ) = ( 0, 0, 0 ) yAll of the internal power supply functions. ( Step Up, Voltage Regulator, Voltage Follower ) ( DC,VR,VF ) = ( 1, 1, 1 ) VDD VDD NJU6682 NJU6682 V1 V2 V3 V4 V5 VOUT VSS + + + + + + V1 V2 V3 V4 V5 VOUT VSS zSome of the internal power supply functions ( Voltage Regulator, Voltage Follower ) ( DC,VR,VF ) = ( 0, 1, 1 ) {Some of the internal power supply functions. ( Voltage Follower ) ( DC,VR,VF ) = ( 0, 0, 1 ) VDD VDD NJU6682 NJU6682 + + + + + + + + + V1 V2 V3 V4 V5 VOUT VSS V1 V2 V3 V4 V5 VOUT VSS ( Caution ) : These switches should be open during the power save mode. NJU6682 (2)Instruction The NJU6682 distinguishes the signal on the data bus D0 to D15 by conbination of A0, RD, and WR(R/W). The decode of the instruction and exection performes only depending on the internal timing only neither the external clock. In case of serial interface, the data input as MSB first serially. The table.4 shows the instruction codes of the NJU6682. Table.4 Code Instruction A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 Description LCD Display ON/OFF D0=0:OFF, D0=1:ON Determine the Line Address of RAM to the COM0. Determine the X Address of Display RAM. Determine the Y Address of Display RAM. (1) (2) (3) (4) (5) Display ON/OFF Z Address Set X Address Set Y Address Set Status Read 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 * Line Address 0 * * X Address Y Address Status 0 Write Data Read Data Status 0 0 Read out the internal status. Write the data into the Display Data RAM Read the data from the Display Data RAM (6) Write Desplay Data (7) Read Desplay Data (8) (9) Normal or Inverse of ON/OFF Static Drive ON/OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 * * * * * * * Start Unit of 1st Block 0 1 0 1 Inverse the ON and OFF Display D0=0:Normal D0=1:Inverse Whole Display Turns ON D0=0:Normal D0=1:Whole Display ON Set the Display Start Unit of Block 1 Set the Display Unit Number of Block 1 Display Unit Number of 1st Block (10) Partial Display 0 0 0 Start Unit of 2nd Block Display Unit Number of 2nd Block Set the Display Start Unit of Block 2 Set the Display Unit Number of Block 2 * The Number of Inverse Line EVR Resister Data Y Address of Display Block 1 0 Display the Status Set the number of inverse line Set the V5 output level to the EVR resister Set Y address of Display block 1 Set the line number of Display block 1 (11) (12) n-Line Inverse Resister Set EVR Resister Set 0 0 0 0 0 0 0 0 0 0 0 * Line Number of Block 1 Y Address of Display Block 2 0 0 0 0 0 * * * * * Line Number of Block 2 Line Number of Block 3 Line Number of Block 4 Line Number of Block 5 Line Number of Block 6 Set Y address of Display block 2 Set the line number of Display block 2 Y Address of Display Block 3 Y Address of Display Block 4 Y Address of Display Block 5 Y Address of Display Block 6 Y Address of Display Block 7 0 0 0 * * Line Number of Block 7 Line Number of Block 8 * 0 1 Y Address of Display Block 8 Set Y address of Display block 3 Set the line number of Display block 3 Set Y address of Display block 4 Set the line number of Display block 4 (13) Variable RAM Mapping Mode 0 0 0 0 0 0 0 0 0 Set Y address of Display block 5 Set the line number of Display block 5 Set Y address of Display block 6 Set the line number of Display block 6 Set Y address of Display block 7 Set the line number of Display block 7 Set Y address of Display block 8 Set the line number of Display block 8 Variable RAM Mapping Mode D0=0:ON D0=1:OFF NJU6682 Code Instruction A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PWM Data (Frame No.1) PWM Data (Frame No.3) PWM Data (Frame No.1) PWM Data (Frame No.3) PWM Data (Frame No.1) PWM Data (Frame No.3) PWM Data (Frame No.1) PWM Data (Frame No.3) * * PWM Data (Frame No.2) PWM Data (Frame No.4) PWM Data (Frame No.2) PWM Data (Frame No.4) PWM Data (Frame No.2) PWM Data (Frame No.4) PWM Data (Frame No.2) PWM Data (Frame No.4) Bias Boost Multiple * 0 1 1 Description Gray Scale Level 0:Set the PWM Data of Frame No.1 and No.2 Gray Scale Level 0:Set the PWM Data of Frame No.3 and No.4 Gray Scale Level 1:Set the PWM Data of Frame No.1 and No.2 Gray Scale Level 1:Set the PWM Data of Frame No.3 and No.4 Gray Scale Level 2:Set the PWM Data of Frame No.1 and No.2 Gray Scale Level 2:Set the PWM Data of Frame No.3 and No.4 Gray Scale Level 3:Set the PWM Data of Frame No.1 and No.2 Gray Scale Level 3:Set the PWM Data of Frame No.3 and No.4 Select Bias (11 types) Set the Boost Multiple :2 to 7 times Increase X Address Counter +1 when writing but no-change when reading 0 0 0 0 0 0 0 0 (15) (16) Bias Select Voltage Converter Multiple Select Read Modify Write /End Reset 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 (14) Select Gray Scale Level (17) (18) 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 D0=0:ON D0=1:END * Initialize the internal circuits (19) Internal Power Supply 0 1 0 0 0 0 1 0 0 1 0 * DC=1:Voltage converter ON DC=0:Voltage converter OFF VR=1:Voltage Regurator ON DC VR VF VR=0:Voltage Regurator OFF VF=1:Voltage Follower ON VF=0:Voltage Follower OFF Set LCD driver outputs after the inter- (20) Driver Outputs ON/OFF Powehr Save (dual command) ADC Select 0 1 0 0 0 0 1 0 0 1 1 * 0 1 0 1 0 1 nal(external) power supply ON D0=0:Driver Outouts OFF D0=1:Driver Outputs ON Set the Power Save mode (Reverse input sequence is possible) Output the Disp. RAM address Sn (21) (22) 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 * * D0=0:Normal D0=1:Reverse (23) Display Mode Select 0 1 0 0 0 0 1 1 0 0 1 * Set Display mode GB=1:Gray scale mode GB=0:Black and white mode GS L1 L0 L1=1:Select layer 1 L1=0:Not select layer 1 L0=1:select layer 0 L0=0:Not select layer 0 * D8=0:Set 8-bit interface bus D8=1:Set 16-bit interface bus (24) 8-bit/16-bit Bus Select 0 1 0 0 0 0 1 1 0 1 0 1 ( * : Don't care) NJU6682 (3)Explanation of Instruction Code 3-1)Display ON/OFF This instruction executes whole display ON/OFF without relationship of the data in the Display Data RAM and internal conditions. (R/W) A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 0 0 0 * * * * * * * D * : Don't Care D=0:Display OFF D=1:Display ON 3-2)Z Address Set This instruction sets the line address of Display Data RAM which correspond to COM0 terminal (Normally, it means the most upper line of the display ). The display area is only the number of lines which is equivalent to display duty in the increasing direction from the line address is automatically. At that time, the data of Display Data RAM isn't changed at all. When the RAM mapping is set to Variable RAM Mapping Mode, the status of Variable RAM Mapping takes priority over this instruction. Therefore, the status of this Z Address Set instruction will be unavailable. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 0 D11 1 D10 0 D9 1 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 R/W A8 A7 0 0 0 0 A6 0 0 A5 0 0 1 1 0 0 0 0 1 1 A4 0 0 : : : 1 1 A3 0 0 A2 0 0 A1 0 0 A0 0 1 1 1 1 1 1 1 0 1 Z Address (HEX) 0 1 : : : 13E 13F NJU6682 3-3)X Address Set In the case of access to the Display Data RAM from MPU side, it is needed that to set the X Address which correspond to Column Address by using of this X Address Set instruction, before data writing. The access to the Display Data RAM is possible by set of both X Address and Y Address. There is no influence to the Display with changing the Y Address. The area of X Address is depended on the Display mode. In gray scale mode, it is from 00H to 10H. In black and white mode, it is from 00H to 08H(layer 0), and from 20H to 28H(layer 1). When Address is set unlike listed above, the Address will be invalid. When MPU accesses to the Display Data RAM continuously, X Address is increased +1 from initial X Address every time RAM is accessed. Therefore, the MPU can access the only Data continuously without resetting of X Address. The increment of X Address is stopped automatically at the point of the maximum value of X Address which is due to each mode +1. At that time, Y Address isn't changed at all. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 * : Don't Care X Address A5 A4 A3 A2 A1 A0 Gray Scale Mode 0 0 0 0 0 0 0 0 0 : : 0 0 1 : : 0 0 0 0 0 1 1 1 0 : : : : 1 1 0 0 0 0 : : 1 1 0 0 0 1 : : : 1 0 1 0 1 0 0 0 0 0 0 1 Address Set is Invalid Layer 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 2 : : : : : 14 15 16 Black & White Mode 0 1 2 : : 8 Layer 0 Address Set is Invalid 32 33 : : 39 40 Address Set is Invalid NJU6682 3-4)Y Address Set In case of access to the Display Data RAM from MPU side, it is needed that to set the Low Address by using of this Y Address Set instruction, in addition to the using of 3-3) the X Address Set instruction is already described, before data writing. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 0 D11 1 D10 0 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 0 0 A7 0 0 A6 0 0 A5 0 0 1 1 0 0 0 0 1 1 A4 0 0 : : 1 1 A3 0 0 A2 0 0 A1 0 0 A0 0 1 1 1 1 1 1 1 0 1 Y Address(HEX) 0 1 : : 13E 13F 7-5)Status Read This instruction reads out the intenal status of "BUSY", "ADC", "ON/OFF", "RESET", "GB" and "LY" are described below. When the extenal bus is set to 8-bit mode, this Status Read instruction will finish in 1 cycle. (R/W) A0 0 RD 0 WR 1 D15 BUSY D14 ADC D13 ON/ OFF D12 RESET D11 GB D10 LY1 D9 LY0 D8 0 D7 BUSY D6 ADC D5 ON/ OFF D4 RESET D3 GB D2 LY1 D1 LY0 D0 0 BUSY :BUSY=1 indicates the operationg or the Reset cycle. This instruction can be input after the BUSY status change to "0". :Indidates the output correspondence of X Address(Segment Address) and Segment Driver. 0:Counterclockwise output (Inverse) 1:Clockwise output (Normal) (Note)The data "0=Inverse" and "1=Normal" of ADC is inverted with the ADC Select instruction of "1=Inverse" and "0=Normal". ADC ON/OFF :Indicates the whole display ON/OFF status. 0:Whole Display "ON" 1:Whole Display "OFF" (Note)The data "0=ON" and "1=OFF" of Display ON/OFF status read out is inverted with the Display ON/OFF instruction data of "1=ON" and "0=OFF". RESET :Indicates the initializing period by RES signal or Reset instruction. 0:Without Reset status 1:In the Reset status GB :Indicates the current Display Mode. 0:Black & White Mode 1:Gray Scale Mode :Indicates the status of Layer 1 when the Display Mode is set to Black & White Mode. 0:Layer 1 isn't selected 1:Layer 1 is selected :Indicates the status of Layer 0 when the Display Mode is set to Black & White Mode. 0:Layer 0 isn't selected 1:Layer 0 is selected LY1 LY0 NJU6682 3-6)Write Display Data This instruction writes the data on the data bus into the Display Data RAM. The X Address increases automatically after data writing, therefore, the MPU can write the data into the Display Data RAM continuously without any address setting after the start address setting. (R/W) A0 1 RD 1 WR 0 D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D15-D0:Write Data 3-7)Read Display Data This instruction reads out the 16-bit data ftom Display Data RAM which addressed by the X Assress and Y Address. The X Address increase "+1" automaticaly after 16-bit data reading out, therefore, the MPU can read out the 16-bit data ftom Display Data RAM continuously without any address setting after the atart address setting. The one time of dummy read must operate after X Address set as the explanation in "(5-4) Access to the Display Data RAM and internal Resister". In the serial interface mode, the display data is not read out. (R/W) A0 1 RD 0 WR 1 D15 D15 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D15-D0:Read Data 3-8)Normal or Inverse ON/OFF Set This instruction changes the condition of display turn ON and OFF as normal or inverse. The contents of Display Data RAM is not changed by this instruction exection. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 D *:Don't Care Black & White Mode: D RAM="1" 0(Normal) LCD ON 1(Inverse) LCD OFF Gray Scale Mode: D RAM="00" 0(Normal) Gray Scale Level 0 1(Inverse) Gray Scale Level 3 RAM="0" LCD OFF LCD ON RAM="01" Gray Scale Level 1 Gray Scale Level 2 RAM="10" Gray Scale Level 2 Gray Scale Level 1 RAM="11" Gray Scale Level 3 Gray Scale Level 0 NJU6682 3-9)Static Drive ON/OFF This instruction turns ON the all pixels independent of the contents of the Display Data RAM. At this time, the contents of Display Data RAM is not changed and kept. This instruction takes precedence over the "Normal or Inverse ON/OFF Set" Instruction. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 D * : Don't Care D=0:Normal Display D=1:Whole Displplay Turns ON If this Static Drive ON/OFF instruction is executed when Display OFF status, the NJU6682 will be in Power Save Mode. The details about this Power Save Mode is descrived in it's own section. 3-10)Partial Display This instrcution devides display area into 40 unit with 4-common each, then display these required area which is selected. Therefore, the duty will be low automatically, so that LCD driving voltage will be low. So, it is suitable when low operating power is requied. *Display Unit Construction UNIT UNIT UNIT UNIT : : : UNIT UNIT UNIT UNIT 0 1 2 3 160-common 36 37 38 39 132-segment When executing the Partial Display function, at first, it must be defined both the Top Unit Number of display area (the Start Unit) and the number of the effective unit start from the Start Unit. And it is possible to set these definition as two blocks. If setting the Start Unit of the 1st Block as "0" (0,0,0,0), and then if setting the Display Unit Number as "40" (1,0,1,0,0,0), it means that to define the all unit of the Display, it becomes that all Display ON (1/160 Duty), and the definition of the 2nd Block will be invalid. And when Partial Display instruction is executed, the duty is changed to optimum condition automaticaly, but LCD Driving Voltage and Bias Voltage aren't changed at all. Therefore, before execution of Partial Display instruction, "Driver Output OFF" instruction must be done, then execute the instruction Bias Set, Voltage Converter Multiple Select, and EVR Resister Set to reset each status with execution of this Partial Display instruction. (Notes) *The Start Unit of the 1st Block must be less than the Start Unit of the 2nd Block. *Don't overlap the 1st Block and the 2nd Block. *The Start Unit of the 1st Block must not be more than 39. *The all Display Unit Number (the sum of the 1st Block Unit Number and the 2nd Block Unit Number) must not be more than 39. *According to a setting, the area is made from the 1st Block to the 2nd Block may be empty, but the Y Address of the Display RAM is continuous. NJU6682 (1)Set the Start Unit of the 1st Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 (2)Set the Display Unit Number of the 1st Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 (3)Set the Start Unit of the 2nd Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 (4)Set the Display Unit Number of the 2nd Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 1 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0 : The Start Unit, or the Display Unit Number Finally, by execution of the command below, it will be changed into the status of the Display have already been defined, and it will be changed into the optimum Duty Ratio. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 1 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 0 * : Don't Care NJU6682 The example and the method of Partial Display are listed below. UNIT 0 UNIT 1 : UNIT UNIT : UNIT UNIT : 14 15 the 1st Block Available Display Area the 2nd Block 28 29 (1)Set the Start Unit of the 1st Block "0". (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 (2)Set the Display Unit Number of the 1st Block "2". (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0 (3)Set the Start Unit of the 2nd Block "14". (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 (4)Set the Display Unit Number of the 2nd Block "16". (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 1 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 Then, the Duty will be changed to 1/128 automatically. (4)Execute the Partial Display (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 1 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 NJU6682 The Sequence about the Partial Display function Driver Output OFF Partial Display n-Line Inverse Set EVR Resister Set Bias Set Voltage Converter Multiple Select (Waiting Time) Driver Outputs O 3-11)n-Line Inverse Resister Set This instruction drives the Display with inverse mode at the specified line. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 1 D8 1 D7 * D6 * D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 * : Don't Care A5 0 0 0 A4 0 0 0 A3 0 0 0 : : 1 1 1 1 1 1 1 1 1 1 0 1 A2 0 0 0 A1 0 0 1 A0 0 1 0 Inverse Line 2 3 : : 63 64 When A5 to A0 are "000000", it will be 2-frame alternating drive mode. NJU6682 3-12)EVR Resister Set This instruction controls Voltage Adjustment Circuit of internal LCD power supply and changes LCD driving voltage "V5". Finally, it adjusts the contrast of LCD display. By setting a data into EVR resister, V5 output voltage selects one condition out of 201-voltage conditions. The range of V5 voltage is adjusted by setting external resister as mentioned in (4-2) Voltage Regulator (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 1 D10 0 D9 0 D8 0 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A7 0 A6 0 A5 1 A4 1 : : A3 0 A2 1 A1 1 A0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 VLCD Low : : : High VLCD=VDD-V5 If EVR isn't used, set the EVR Resister to (1,1,1,1,1,1,1,1). NJU6682 3-13)Variable RAM Mapping Mode At this Variable RAM Mapping Mode, it is possible to define the RAM area in a maximum of 8-blocks not to continue to display the screen. Therefore, it is easy to replace a part of the Display Data each other(Fig.7, 8). When using this Variable RAM Mapping Mode, the Z Address is defined by "3-2)Z Address Set instruction" will be invalid. So, Vertical Scroll with changing a Z Address will be unable. And, it is available to define the Display Line Number of each blocks as "1" to "63", but it must not define as "0". If setting the all Display Line Number more than the Duty, the line data which is over the Duty will not be displaied. After Reset is executed, the resister about this Variable RAM Mapping Mode will be indefinite. 1st Block Y Address A 2nd Block Y Address 3rd Block Y Address 4th Block Y Address 1st Block Display Line Number A B B C D 2nd Block Display Line Number 3rd Block Display Line Number 4th Block Display Line Number 5th Block Display Line Number 6th Block Display Line Number 7th Block Display Line Number C D E F G 5th Block Y Address 6th Block Y Address E F 7th Block Y Address H G 8th Block Y Address H 8th Block Display Line Number Fig.7-1 The setup of Variable RAM Mapping Mode, and the Address Map Fig.7-2 The actual view of the Display NJU6682 The Example of Variable RAM Mapping Mode 1st Block Y Address A 1st Block Display Line Number 3rd Block Y Address B 3rd Block Display Line Number Y Address=80H Y Address=100H C D Fig.8-1 The setup of Variable RAM Mapping Mode, and the Address Map A C A D A C B B B Fig.8-2 The actual Views of the Display when the 2nd Block Y-Address is changed like the sequence of "80"H -> "100"H -> "80"H NJU6682 (1)Set the Y Address of the 1st Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 0 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 1st Block (0 to 319) (2)Set the Display Line Number of the 1st Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 1st Block (1 to 63) (3)Set the Y Address of the 2nd Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 1 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 2nd Block (0 to 319) (4)Set the Display Line Number of the 2nd Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 1 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 2nd Block (1 to 63) (5)Set the Y Address of the 3rd Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 0 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 3rd Block (0 to 319) (6)Set the Display Line Number of the 3rd Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 3rd Block (1 to 63) (7)Set the Y Address of the 4th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 1 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 4th Block (0 to 319) (8)Set the Display Line Number of the 4th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 1 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 4th Block (1 to 63) NJU6682 (9)Set the Y Address of the 5th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 0 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 5th Block (0 to 319) (10)Set the Display Line Number of the 5th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 5th Block (1 to 63) (11)Set the Y Address of the 6th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 1 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 6th Block (0 to 319) (12)Set the Display Line Number of the 6th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 1 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 6th Block (1 to 63) (13)Set the Y Address of the 7th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 0 D9 1 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 7th Block (0 to 319) (14)Set the Display Line Number of the 7th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 7th Block (1 to 63) (15)Set the Y Address of the 8th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 1 D9 0 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 A8 to A0:the Y Address of the 8th Block (0 to 319) (16)Set the Display Line Number of the 8th Block (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 1 D9 1 D8 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 * : Don't Care D5 to D0:the Display Line Number of the 8th Block (1 to 63) NJU6682 By using of the following instruction, Variable RAM Mapping Mode will be executed. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 1 * : Don't Care And, by using of the following instruction, it will go back to the normal status from Variable RAM Mapping Mode. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 0 * : Don't Care NJU6682 3-14)Gray Scale Level Select This instruction sets the level of 4-gray scale. The setting of each gray scale level is executed by writing the PWM data (0 to FH) to the 4-Resisters of the 4-Flames consists of 1st to 4th. And, among the 4-gray scale levels, the level 0 corresponds to the data (0,0) of the Display Data RAM, the level 1 is the data (0,1), the level 2 is the data (1,0), and the level 3 is the data (1,1). Just after Reset, a Resister is related to the Gray Scale Level Select will be initialized like a following table. PWM Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F Gray Scale Level 0/15(initialized value of level 0) 1/15 2/15 3/15 4/15 5/15(initialized value of level 1) 6/15 7/15 8/15 9/15 10/15(initialized value of level 2) 11/15 12/15 13/15 14/15 15/15(initialized value of level 3) (1)Set the PWM Data of both the 1st Frame and the 2nd Frame with the Gray Scale Level 0. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 D13 D6 D12 D5 D11 D4 D10 D3 D23 D2 D22 D1 D21 D0 D20 D13 to D10 : the PWM Data of the 1st Frame D23 to D20 : the PWM Data of the 2nd Frame (2)Set the PWM Data of both the 3rd Frame and the 4th Frame with the Gray Scale Level 0. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 D33 D6 D32 D5 D31 D4 D30 D3 D43 D2 D42 D1 D41 D0 D40 D33 to D30 : the PWM Data of the 3rd Frame D43 to D40 : the PWM Data of the 4th Frame (3)Set the PWM Data of both the 1st Frame and the 2nd Frame with the Gray Scale Level 1. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 1 D8 0 D7 D13 D6 D12 D5 D11 D4 D10 D3 D23 D2 D22 D1 D21 D0 D20 D13 to D10 : the PWM Data of the 1st Frame D23 to D20 : the PWM Data of the 2nd Frame (4)Set the PWM Data of both the 3rd Frame and the 4th Frame with the Gray Scale Level 1. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 1 D8 1 D7 D33 D6 D32 D5 D31 D4 D30 D3 D43 D2 D42 D1 D41 D0 D40 D33 to D30 : the PWM Data of the 3rd Frame D43 to D40 : the PWM Data of the 4th Frame NJU6682 (5)Set the PWM Data of both the 1st Frame and the 2nd Frame with the Gray Scale Level 2. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 0 D8 0 D7 D13 D6 D12 D5 D11 D4 D10 D3 D23 D2 D22 D1 D21 D0 D20 D13 to D10 : the PWM Data of the 1st Frame D23 to D20 : the PWM Data of the 2nd Frame (6)Set the PWM Data of both the 3rd Frame and the 4th Frame with the Gray Scale Level 2. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 0 D8 1 D7 D33 D6 D32 D5 D31 D4 D30 D3 D43 D2 D42 D1 D41 D0 D40 D33 to D30 : the PWM Data of the 3rd Frame D43 to D40 : the PWM Data of the 4th Frame (7)Set the PWM Data of both the 1st Frame and the 2nd Frame with the Gray Scale Level 3. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 1 D8 0 D7 D13 D6 D12 D5 D11 D4 D10 D3 D23 D2 D22 D1 D21 D0 D20 D13 to D10 : the PWM Data of the 1st Frame D23 to D20 : the PWM Data of the 2nd Frame (8)Set the PWM Data of both the 3rd Frame and the 4th Frame with the Gray Scale Level 3. (R/W) A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 1 D8 1 D7 D33 D6 D32 D5 D31 D4 D30 D3 D43 D2 D42 D1 D41 D0 D40 D33 to D30 : the PWM Data of the 3rd Frame D43 to D40 : the PWM Data of the 4th Frame NJU6682 3-15)Bias Select This instruction sets the Bias Voltage. And it must be done with the setting of the Partial Display Mode. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 1 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 A3 D2 A2 D1 A1 D0 A0 * : Don't Care A3 0 0 0 0 0 0 0 0 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 * A1 0 0 1 1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 1 0 1 * *: Don't Care Bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12 1/13 1/14 3-16)Voltage Converter Multiple Select This instruction sets the boost level multiple of Internal Voltage Converter Circuits(2-times to 7-times). It must be done with the setting of the Partial Display Mode. If the external capasitor is connected as the boost level multiple is lower than 6-times, don't select the multiple with this instruction over its multiple is owing to its connection of the external capacitor. There is a fear of an incorrect function. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 * D2 A2 D1 A1 D0 A0 * : Don't Care A2 0 0 0 0 1 1 3-17)Read Modify Write A1 0 0 1 1 0 * A0 0 1 0 1 0 1 Boost Multiple 2-times 3-times 4-times 5-times 6-times 7-times * : Don't Care This instruction sets the Read Modify Write Mode for the page address increment control. In this mode, the X Address insreases "+1" automatically when the Display Data Write instruction is exexuted, but the X Address doesn't change when the Display Data Read Instruction is executed. This status is continued until the End instruction execution. When the End instruction is executed, the X Adddress goes back to the start address before the execution of this Read Modify Write instruction. This function reduces the load of MPU for repeating the display data change in the fixed area(ex. cursor blink). (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 D * : Don't Care D=0:Read Modify Write ON D=1:End (Note)In mode of this Read Modify Write, any instructions except Y Address Set can execute. NJU6682 The Example of Read Modify Write Sequence Executed Instructions Display Contents (In 8-bit bus mode, indicates the X Address) Y Address Set Set the Start Address of the Cursor Display *1 X Address Set N N+1 N+2 N+3 Start Read Modify Write the Read Mdify Write The data will be ignor Dummy Read X Counter does't increase Data Read X Counter does't increase Read out the data The data is inversed at MPU Write back the data N N+1 N+2 N+3 Data Write X Counter increase "+1" Dummy Read Data Read Data Write Repeat the same X Counter doesn't increase sequence X Counter doesn't increase X Counter increase "+1" X Counter doesn't increase X Counter doesn't increase N N+1 N+2 N+3 Dummy Read Data Read Data Write X Counter increase "+1" X Counter doesn't increase X Counter doesn't increase X Counter increase "+1" N N+1 N+2 N+3 N+4 Dummy Read Data Read Data Write N N+1 N+2 N+3 N+4 End the Read Modify Write End X Counter is reset to Finish ? Yes the value of *1 N N+1 N+2 N+3 N+4 No NJU6682 3-18)Reset This instruction executes the following initialization. Initialization 1:Clear the Resister of the Selial Interface. 2:Set the X Address Counter (00)H. 3:Set the Y Address Resister (000)H. 4:Set the Z Address Counter (000)H 5:Normal RAM Address Mapping(Variable RAM Mapping Mode OFF). 6:Set the EVR Resister (FF)H. 7:Set the Duty "1/160"(All ON). 8:Set the Bias Select "1/14". 9:Set the Voltage Boost Multiple "7-times". 10:Set the n-Line Inverse Resister (0)H. 11:Set the Bus 8-bit Bus Mode. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 D * : Don't Care At this time, the Display Data RAM is not influenced. The reset signal input to the RES terminal ( hardware reset ) must be input for the power on intialization. Reset instruction does not perform completely instead of hardware reset using the RES terminal. 3-19)Internal Power Supply This instruction set ON/OFF of Voltage Converter, Voltage Regulator and Voltage Follower. To operate the Voltage Converter, the oscillation circuits must be operating. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 * D2 DC D1 VR D0 VF * : Don't Care DC=1:Voltage DC=0:Voltage VR=1:Voltage VR=0:Voltage VF=1:Voltage VF=0:Voltage 1)At Converter ON 1) Converter OFF Regulator ON 2) Regulator OFF Follower ON 3) Follower OFF terminals C1+,C1-,C2+,C2-,C3-,C4-,C5- and C6- should be open, should be supplied from outside. terminal VR should be open, and V5 should be supplied from outside. terminals V1 to V5 should be supplied from outside. this time, and VOUT 2)At this time, 3)At this time, The time which is needed for complitely starting up of the Internal Power Supply is depending on each settings (Supply Voltage, VLCD=VDD-V5, External Capacitor of Voltage Converter, External Capacitor which is connected to V1 to V5). To know the time corretly, the test with actual LCD module must be needed. NJU6682 3-20)Driver Outputs ON/OFF This instruction controlls ON/OFF of the LCD Driver Outputs. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 1 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 D * : Don't Care D=0:Driver Outputs OFF(No signal is output) D=1:Driver Outputs ON(Signal is output) The NJU6682 contains low power LCD driving voltage generator circuit reducing own operating current. Therefore, it requires the following sequence procedures at power on for power source stabilized operation. qLCD Driving Power Supply ON/OFF Sequences The following sequences are required when the power supply is turned ON/OFF. When the Power Supply is turned on again after the turn off (by the Power Save instruction), the power save release sequence(s) is required. Turn ON Sequence Turn OFF Sequence Output Assign Register Set Display OFF EVR Resister Set Static Drive ON Internal Power Supply ON or External Power Supply ON Internal Power Supply ON or External Power Supply ON (Wait Time) Driver Outputs OFF Driver Outputs ON NJU6682 3-21)Power Save When both of Display OFF and Static Drive ON are executed( its sequence is not required ), the internal circuits go to the Power Saving Mode and the operating current is reduced as same as the stand by current. The internal status in this Power Save Mode is shown in follows; 1:The operation of both the Oscillation Circuits and the Internal Power Supply Circuits is stopped. 2:LCD driving is stopped. Segment and Common drivers output Vdd level voltage. 3:Both the display data and the operating mode just before the Power Save Mode is kept. 4:All of the LCD driving bias voltage is fixed to the VDD level. *1 In the Power Save sequence, the Power Save Mode is started after the second instruction (Static Drive ON). *2 In the Power Save release sequence, the Power Save Mode is released after the Static Drive OFF instruction.The Display ON instruction can input at any timming after the Static Drive OFF instruction in Power Save release sequence. *3 LCD driving signal isn't output until the xexection of the Driver Outputs ON instruction. *4 In case of the external power supply for LCD driving, it should be turn off and made condition like as disconnection or connection to VDD before the Power Save Mode or at the same time. In this time, VOUT terminal should be made codition like as disconection or connection to the lowest voltage of the system. Power Save Sequence Display OFF Power Save Release Sequence Static Drive OFF Static Drive ON Display ON (Wait Time) Driver Outputs OFF Driver Outputs ON NJU6682 spends the current regularly without the execution of the Driver Outputs OFF instruction. The LCD drive signal will not be output until the Driver Outputs ON instruction is done. 3-22)ADC Select This instruction defines the correspondence of X Address of the display RAM with the Segment Driver Outputs. By using of this instruction, it is possible to invert the sequence of the Segment Driver Output. Therefore, the limitation like a arrangement of IC with LCD module making will decrease. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 D * : Don't Care D=0:Clockwise Output (Normal) D=1:Counterclockwise Output (Inverting) NJU6682 3-23)Display Mode Select This instruction selects the Display Mode. (R/W)S A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 GS D1 L1 D0 L0 * : Don't Care GS=1:Gray Scale Mode GS=0:Black & White Mode When GS=0(Black & White Mode), the following L1 and L2 bit are valid. L1=1:Select the L1=0:Not select L0=1:Select the L0=0:Not select Layer 1 the Layer 1 Layer 0 the Layer 0 3-24)8-bit/16-bit Bus Select This instruction sets the interface bus as 8-bit or 16-bit. (R/W) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 1 D10 0 D9 1 D8 D D7 * D6 * D5 * D4 * D3 * D2 * D1 * D0 * * : Don't Care D=0:Select 8-bit interface bus (D7 to D0). D=1:Select 16-bit interface bus (D15 to D0) NJU6682 (4)Internal Power Supply 4-1)7-Time Voltage Booster circuits 7-time voltage booster circuit connecting seven capacitors between C1+, C1- and C2+, C2- and ,C3-,C4-, C5- and C6- ,VSS and VOUT boost the voltage of VDD-VSS to negative Voltage(VDD Common) and output the boosted voltage from VOUT terminal. It selects one of boost time from 2 to 7 times by external capacitors connection.Furthermore,it also selects one of boost time by "Voltage Booster circuits mulitiple select" instruction.The boost voltage and the voltage booster circuits are shown below. Voltage Booster circuits requires the clock signals from internal oscillation circuit,therefore ,the oscillation circuits must be operating when voltage boost operation. The boost voltage times are shown in below. When 7 times boost operation,the operation voltage of VDD-VOUT should be less than 18V. The relationship with Boosted voltage and VDD,VSS VDD=+3V VSS=0V VOUT=-VDD=-3V VOUT=-2VDD=-6V VOUT=-3VDD=-9V VOUT=-4VDD=-12V VOUT=-5VDD=-15V VOUT=-6VDD=-15V VDD=+2.5V 2-Time 3-Time 4-Time 5-Time 6-Time 7-Time Example of Capacitor connection in voltage Booster circuits 7-Times VSS C1+ C1C2+ C2C3C4C5C6VOUT 6-Times VSS C1+ VSS C1+ 5-Times + + + + + + + C1C2+ C2C3- + + + C1C2+ + + + + + C2C3C4C5- + C4C5C6VOUT + + C6VOUT 4-Times VSS C1+ C1C2+ C2C3C4C5C6VOUT VSS C1+ 3-times 2-times VSS C1+ C1+ + + C1C2+ + C2+ + + C2C3C4C5C6VOUT + + C2C3C4C5C6VOUT + NJU6682 4-2)Voltage Adjust Circuit The boosted voltage of VOUT output from V5 through the voltage adjust circuits for LCD driving. The output voltage of V5 is adjusted by changing the Ra+Rb within the range of |V5| < |VOUT|. The output is calcurated by the following fomula(1). VLCD=VDD-V5=(1+Rb/Ra)*VREG ------------------------------------------(1) The voltage of VREG is a standard voltage produce from built-in bleeder registance.VREG is possibleto be fine-adjusted by EVR functions mentioned in(4-3). For fine-adjustment of V5,R2 as variable resistor,R1 and R3 as fixed constant should be connectedto VDD terminal,VR and V5 ,as shown below. VDD Vreg Ra + Vr - V5 Rb < Design example for R1, R2 and R3 /Reference > *R1+R2+R3=5M (Determind by the current flown between VDD-V5) *Variable voltage range by the R2. 6V to 7.5V (VLCD=VDD-V5) (Determind by the LCD electrical characteristics) *VREG=3V (In case of VDD=3V) R1,R2 and R3 are calculated by above conditions and the fomula of(1) to below; R1=2.0M R2=0.5M R3=2.5M Note) If the power supply voltage between VDD and VSS changes,V5 changes too.therefore the power supply voltage should be stabilized for V5 stable operation. NJU6682 4-3)Contrast adjustment by the EVR function The EVR control voltage of VREG by instruction and changes voltage of V5. AS result,LCD Display contrast is adjusted by V5.The EVR selects a voltage of VREG in the following 201 conditions by setting 8 bits data into the EVR register. A step with EVR is set like table shown below. EVR register (37)h (38)h (39)h : : : : (FD)h (FE)h (FF)h VREG (100/300) x (VDD-VSS) (101/300) x (VDD-VSS) (102/300) x (VDD-VSS) : : : : (298/300) x (VDD-VSS) (299/300) x (VDD-VSS) (300/300) x (VDD-VSS) When using an EVR function, the voltage adjustment circuit must be turn on by the power supply instruction. qAdjustable range of the LCD driving voltage by EVR function The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors. Example) NJU6682 Condition:VDD=3.0V Ra=1M, Rb=4M (Ra:Rb=1:4) The adjustable range and step voltage are calculated as follows in the above condition. In case of setting 37(H) in the EVR register, VLCD=(1+Rb/Ra) x VREG =(1+4) x (100/300) x 3.0 =5.0 In case of setting FF(H) in the EVR register, VLCD=(1+Rb/Ra) x VREG =(1+4) x (300/300) x 3.0 =15.0 NJU6682 4-4)LCD Driving Voltage Generation Circuit The LCD driving bias voltage of V1,V2,V3,V4 are generated internally by dividing the V5 voltage with the internal bleeder resistance.And it is supplied to the LCD driving circuits after the impedence conversion with voltage follower circuit. As shown Fig-3,Five capacitors are required to connect to each LCD driving voltage terminal for voltage atabilizing. And the value of C7 to C11 are determind depending on the actual LCD panel display evaluation. In case of Internal Power Supply In case of using External Power Supply VSS + C1 + C2 + C3 + Cout + + C5 + + C6 + C6Vout R3 V5 V5 NJU6682 *2 C5+ C4C3C3C4C5C6NJU6682 Vout C1+ C1C2+ C2VSS C1+ C1C2+ C2- C4 *1 R2 VR VR R1 VDD VDD + + + + + C7 C8 C9 C10 C11 V1 V2 External V3 V4 V5 Power Supply V1 V2 V3 V4 V5 Fig-3 *1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR Terminal. *2 Following connection of VOUT is required when external power supply using. When VSS>V5 --- VOUT=V5 When VSSV5 --- VOUT=VSS Reference set up value VLCD=VDD-V59.0 to 10.5V COUT C1 to C6 C7 to C11 R1 R2 R3 ~1.0uF ~1.0uF 0.1~0.47 uF 2M 500K 2.5M NJU6682 (b) Interface with 16 bit MPU (16 bit BUS Interface Mode) A0 Terminal WR Termin RD Terminal D15 to D8 Terminal D7 to D0 Terminal Write Instruction BUSY Flag Check (Status read) Write Display Data Dummy Read Read Display Data D15toD8 D7toD0 Status Status D15toD8 D7toD0 D15toD8 D7toD0 D15toD8 D7toD0 5-3) Serial Data Input (PS1="L") In the serial interface of NJU6682 consists 16-bit shift register and 4-bit counter, In case of chip select (CS=L) means it becomes to input D7(SI) and D6(SCL), and in case of chip isn't select, a shift register and a counter are reset to the initial condition. The data input from terminal(SI) is MSB first like as the order of D15, D14, ***D0 by a serial interface, it is entered into with rise edge of serial clock(SCL). The data converted into parallel data of 16-bit with the rise edge of 16th serial clock and processed. The serial interface of NJU6682 can two way select to 3-wire type and 4-wire type by PS0 terminal. In choosen PS0 terminal to "H", it become 4-wire interface and discliminate display data, instructions by A0 input terminal. A0 is read with rise edge of (16 X n)th of serial clock (SCL), it is recognize display data by A0=H" and instruction by A0="L". A0 input is read in the rise edge of (16 X n)th of serial clock (SCL) after chip select and distinguished. However,in case of RES="L" or CS="H" with trasfered data does not fill 16 bit, attention is necessary because it will processed as there was command input. Always, input the data of (16 X n) style. In choosen PS0 terminal to "L",it becomes 3-wire interface and discleminate data after the serial data of 16-bit as the A0 data. Note) The SCL signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it. NJU6682 (a) 4-wired Serial Interface CS First transfer data Next transfer data SI D15 D14 D13 D12 D1 D0 D15 D14 SCL 1 A0 2 3 4 15 16 17 18 Fig 4-1 A0="H": Display Data A0="L": Instruction (b) 3-wire Serial Interface CS First transfer data Next transfer data SI D15 D14 D13 D12 D1 D0 A0 D15 SCL 1 2 3 4 15 16 17 18 Fig 4-2 A0="1":Display Data A0="0":Instruction 5-4)Display Data RAM , Access of Internal Register NJU6682 communicates with the CPU through bus holder with the internal data BUS. In case of reads the display data contents in Data RAM, the data which was read in the first data read cycle ( the dummy read ) is memorized in bus holder and is read on the system BUS from BUS holder in the following data read cycle. Also, In case of MPU writes into Display Data RAM, after once maintained by bus holder, it is written Into Display Data RAM by the following data write cycle. Therefore, the restrict in case of access by NJU6682 which was seen from MPU side is not access time (tACC,tDS) of Display Data RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the MPU becomes possible. In case of cycle time isn't met, the MPU inserts NOP operation and becomes equivalent to for this to execute wait operation on sutisfy condition.In MPU . But, there is an restricts in the read sequence of Display Data RAM. When setting an address, the data of the specified address isn't output by the read operation immediately after setting an address and the data of the specification address is output at the the 2nd data read. Therefore, the dummy read is always necessary once after address set and the write cycle. NJU6682 sASOLUTE MAXIMUM RATING PARAMETER Supply Voltage(1) Supply Voltage(2) Supply Voltage(3) Input Voltage Operating Temperature Strage TCP Temperature Bare chip SYMBOL VDD V5 , VOUT V1,V2,V3,V4 VIN TOPR TSTG RATINGS -0.3 to +5.0 VDD-20.0 to VDD+0.3 V5 to VDD+0.3 -0.3 to VDD+0.3 -30 to +80 -55 to +100 -55 to +125 UNIT V V V V C C VDD VSS VDD V5 (Note 1) Voage values are specified as VSS=0. (Note 2) Inase of using voltage boost circuit, as for the supply voltage, conditioned of 18.0VVDD-VOUT (Note 3) The relation VDDV1V2V3V4V5;VDD>VSSVOUT must be maintained. When inputting external LCD driving voltage , LCD drive voltage is simultaneous with the rise of VDD power supply or after rises VDD. (Note 4) If the LSI are used on condition above the absolute maximum rating,the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the erectric characteristics conditions will cause malfunction and poor reliability. (Note 5) Decoupling capacitor should be connected between VDD and VSS due to stabilized operation for the Voltage Converter. NJU6682 sELECTRICAL CHARACTERISTICS PARAMETER Operating voltage(1) SYMBOL CONDITIONS VDD V5 Operating Voltage(2) V1,V2 V3,V4 Input High Level VIHC1 Voltage Low Level VILC1 Output High Level VHC11 Voltage Low Level VOLC11 Input Leagage Current ILI0 VLCD=VDD-V5 A0,D0-D15,RD,WR,RES,CS Exclude P/S, SEL68,OSC1 terminal D0toD1 Terminal IOH=-0.5mA IOL= 0.5mA (VDD=2.4 to 3.3V, VSS=0V, Ta=-30 to +80C) MIN TYP MAX UNIT NOTE 2.4 3.3 V 1 VDD-18.0V VDD-6.0V V 2 VDD-0.5VLCD VDD V5 VDD - 0.5VLCD 0.8VDD VDD V VSS 0.2VDD 0.8VDD VDD V VSS 0.2VDD -1.0 2.0 T.B.D 10 T.B.D 1.0 10 1.0 3.0 T.B.D A k A pF kHz S S 7 8 3 4 6 Driver On-resistance RON Stand-by Current Input Terminal Capacitance Oscillation Frequency Reset Time Reset "L" level pulse Width Voltage boost output voltage Voltage boost On-resistance Adjustment range of LCD driving Voltage Voltage Follower Operating Current In use external Power supply IDDQ CIN fOSC tR tRW All input terminal, D0 to D15 Terminal in High Z Ta=25C VLCD=15V During Power Save Mode Ta=25C VDD= 3.0V, Ta=25C RES terminal VOUT1 RTRI VOUT2 V5 IDD01 IDD02 7-times boost, VDD=2.5V 7-times boost, VDD=2.5V,Cout=4.7F Voltage boost operation off Voltage adjustment circuit "OFF" Display VLCD=16V Access fCYC=200KHz VDD-17.5V VDD-17.0V 3.0 V k V V A 9 VDD - 8.0V VDD - 18.0V TBD TBD VDD - 6.0V VDD - 6.0V TBD TBD 10 A % 11 Operating Current In use internal power supply IDD VREG% Display VDD=3V,VLCD=16V , 6-time boost COn/Sn are Open , non-access , Display Checkerd pattern VDD=3.0V, Ta=25C 300 TBD T.B.D Voltage Regulator *1:NJU6682 can ooerate wide operating rangr,but it is not guarantee immideate voltage changing during the accessing of the MPU. *2:The operating current in use external power supply. *3:RON is the resistance values beteen power supply terminals (V1,V2,V3,V4) and each output terminals of common and segment suppliedby 0.1V. This is specified within the range of supply voltage(2). *4,5:In case of not use internal power supply circuit,meaning current of IC's. LCD driving power supply are external power supply. *4,5,11:The value of after execute driver output-oninstruction. *4:Apply no access from MPU. *5:The operating current when always writing a vertical stripe pattern in tcyc. In accessing current is proportional to the access frequency approximately. When not accessed, I become only IDD01. *6:Apply A0,D0toD15,RD,WR,CS,RES,SEL68,PS0,PS1 terminals. *7:tR ( the reset time ) shows the time of the inner circuit reset completion from the rise edge of the RES signal. NJU6682 *8:Apply minimum pulse width of the RES signal. To operate the reset, the "L" pulse over tRW must be inputted.RES. *9:The voltage adjustment circuit controls V5 in the voltage follower operation voltage *10:Each operating current is defined as being measured in the following condition. POWER SUPPLY SET INSTRUCTION SYMBOL DC VR VF IDD1 1 1 1 OPERATING CONDITION Internal Oscillator Validity Voltage Booster Validity (6-time boost) Voltage Adjustment Validity V/F Circuit Validity EXTERNAL VOLTAGE SUPPLY (INPUT TERMINAL) Unuse *LCD output terminal Open. *Display on,Display checered pattern,No access from MPU *Set VLCD=16V *Set to R1+R2+R3=2M Mesurment Block Diagram :IDD1 R1 VR VDD R2 R2 V5 NJU6682 A VSS C1C1+ C3C5C2C2+ C4C6VOUT + + + + + + + NJU6682 *11:As for power supply VREG, provide by the error of the VLCD output with the electronic volume. It use the measurement system shown below. VDD NJU6682 Ra VR X V Rb X V5 VREG%=(VREAL-VIDEAL)/VIDEALX100 - VIDEAL means a ideal value and VREAL means a measurement value. - As for the calculation of VIDEAL, refer to voltage adjustment circuit (6-9-11), the voltage adjustment circuit (6-9-11) which used an electronic volume function. Vout *12:The voltage change by the output current prescribes a range within Vlcd X 5%. VLCD=12.0V;(VDD-Vout)=16.0V. It define a measurement system shown below. *:Vn shows either of V1-V5 measurement terminal. V/F current supply performance is reduceed to the minimize because of the low consumption current. Therefore, when measuring, the current which flows through the voltmeter in the figure, too, becomes not able to be ignored. When measuring, it requeire enough consideration. V VDD Vn NJU6682 A NJU6682 A Vn V V5 Measurement circuit for Source current Measurement circuit for Sink current NJU6682 sBUS TIMING CHARACTERISTICS *Read/Write operation sequence(80 type MPU) tCYC8 A0 tr tAW8 WR,RD (CS) D0 to D8 D0 to D15(16 bit BUS Mode) (Write) D0 to D8 D0 to D15(16bit BUS Mode) (Read) tf tAH8 tCCL tCCH tDS8 tDH8 tACC8 tOH8 PARAMETER Address Hold Time Address Set up Time System Cycle Time (WRITE) System Cycle Time (READ) Control Pulse Width (WR) Control Pulse Width (RD) Control "H" Pulse Width Data Set Up Time Data Hold Time Rdaccess Time Output Disable Time Rise Time / FallTime SIGNAL A0,CS SYMBOL tAH8 tAW8 tCYC8(W) WR tCYC8(R) tCCL(W) RD tCCL(R) WR,RD tCCH tDS8 D0 to D7 tDH8 D8 to D15 tACC8 tOH8 CS,WR,RD tr, tf (VDD=2.4V to 3.3V, Ta=-30 to 80C) Measurement MIN TYP MAX UNIT Condition 0 0 160 360 50 250 ns 110 30 5 240 CL=100pF 0 50 15 *1 All timing based on 20% and 80% of VDD. NJU6682 *System BUS Sequence (Read / Write) (68-type MPU) tCYC6 E tr tEWL R/W tAW6 A0,CS tAH6 tEWH tf D0 to D7, D8 to D15(16 bit BUS Mode (Write) D0 to D7, D8 to D15(16 bit BUS Mode) (Read) tACC6 tDS6 tDH6 tOH6 PARAMETER Address Hold Time Address Set Up time System Cycle Time (WRITE) System Cycle Time (READ) READ WRITE Enable "L" PilseWidth (READ/WRITE) Data Set Up Time Data Hold Time Access Time Output Disable Time Rise Time / Fall Time Enable "H" Pulse Width SIGNAL A0,CS R/W SYMBOL tAH6 tAW6 tCYC6(W) tCYC6(R) tEWH E tEWL tDS6 D0toD7, tDH6 D8toD15 tACC6 tOH6 tr, tf E (VDD=2.4V to 3.3V, Ta=-30 to 80C) Measurement MIN TYP MAX UNIT Condition 0 0 160 360 250 50 ns 110 30 5 240 CL=100pF 0 50 15 *1 All timing are based on 20% and 80% of VDD. *2 tCYC6 shows the cycle of the E signal to place in the in active CS. NJU6682 *Serial Interfave CS tCSS tCSH A0 tSAS tSAH SCL tSCYC1 tSLW tf tr tSDS tSDH tSHW SI (VDD=2.4V to 3.3V, Ta=-30 to 80C) PARAMETER Serial Clock Cycle Instruction Input 2) SIGNAL SYMBOL tSCYC1 Measurement Condition MIN 60 200 30 30 15 15 15 15 30 30 TYP MAX UNIT Instruction Time* SCL"H" Pulse Width SCL"L" Pilse Width Address Set Up Time Address Hold Time Data Set Up Time Data Hold Time CS-SCLTime Rise Time / Fall Time SCL A0 SI CS SCL tSCYC2 tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tf, tr ns 15 *1 All timing are based on 20% and 80% of VDD. *2 When inputting an instruction continuously, provide the cycle of SCL among the instructions as follows by 200 nS. SCL 16 Clock(4-wire) th SCL 17 Clock(3-wire) th st SCL 1 Clock SCL tSCYC2 (200nS) SCL"L"Pulse Width (Instruction Time) Instruction (n th) Instruction (n+1 th) NJU6682 sLCD Driving Wave Form (Black & Whitr Mode) FR VDD VSS VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C0 C1 C2 S0 S4 S3 S2 S1 S0 S1 C0-S0 C0-S1 Fig 4 NJU6682 sAPPLICATION CIRCUIT MPU Interface Example NJU6682 can direct connection with 80 type MPU and 68 type MPU. Moreover, with to use a serial interface, it is possible to control by the signal line with the more small being. *:CEL68 terminal should be connect VDD or VSS. *80 type MPU Vcc A0 A0 to A7 A0 VDD SEL68 Decoder CS MPU IORQ D0 to D7 D8 to D15 RD WR GND RES RESET D0 to D7 D8 to D15 RD WR RES NJU6682 VDD PS1 PS0 VDD or GND VSS *68 type MPU Vcc A0 A0 to A15 A0 VDD SEL68 VDD Decoder CS MPU VMA D0 to D7 D8 to D15 E R/W GND RES RESET D0 to D7 D8 to D15 E R/W RES NJU6682 VDD PS1 PS0 VDD or GND VSS *Serial Interface (4-Wire) Vcc A0 A1 to A7 A0 VDD SEL68 Decoder CS MPU Port 1 Port 2 D7(SI) D6(SCL) NJU6682 PS1 VDD or GND PS0 RES RESET RES VDD GND VSS MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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